Refine your search
Collections
Co-Authors
Year
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z All
Bayadi, Hassan
- A Simulation Environment for Network Processor Based on Simultaneous Multi Thread Architecture
Abstract Views :499 |
PDF Views:97
Authors
Affiliations
1 Department of Electrical Engineering, Islamshahr Branch, Islamic Azad university, Tehran, IR
2 Department I.E Engineering Sience&Technology, Mazandaran university, Mazandaran, IR
3 Department of electrical engineering, East Tehran Branch IslamicAzad University, Tehran, IR
1 Department of Electrical Engineering, Islamshahr Branch, Islamic Azad university, Tehran, IR
2 Department I.E Engineering Sience&Technology, Mazandaran university, Mazandaran, IR
3 Department of electrical engineering, East Tehran Branch IslamicAzad University, Tehran, IR
Source
Indian Journal of Science and Technology, Vol 5, No 10 (2012), Pagination: 3384-3389Abstract
This study is centered on the architectural efficacy of network processors based on simultaneous multi thread (SMT) architecture that support multiple active concurrent hardware threads at the same time with the goal of sharing processor resources such as functional units and memory. This thread-level-parallelism can be exploited in packet processing devices called network processors. The programs running on network processors have different characteristics depending on where the processor is used and the input workload. In this paper , we introduce our simulation environment, called SNP (Simulator for Network Processor), for simulating a typical SMT network processor which includes a connected network controller and a packet generator. The simulator presented in this study is a process based "simulator for Network processor" (SNP) usable for different modes and applications based on "clock - by - clock" method and is described according to SMT Structure. The simulator architecture is performed by C++ language optimized as efficient as possible. Such simulator is similar with simple scalar simulator.Keywords
Network Processor, Router, Packet, Simulator, Architectural EfficacyFull Text
References
- Burger D and Austin T (1997) The SimpleScalar Tool Set, v2.0. Technical Report UW-CS-97-1342, University of Winsconsin, Madison.
- CISCO (1999) Router architecture session 601, cisco system ,Inc,
- Franklin MA and Joshi V (2004) SimplePipe: a simulation tool for task allocation and design of processor pipelines with application to network processor. The IEEE Computer society 12th annual international symposium on modeling analysis and simulation of computer and telecommunications systems, Washington Univ., USA. pp: 59-66..
- Gries M, Kulkarni C, Sauer C and Keutzer K (2003) Comparing analytical modeling with simulation for network processor. Design Automation and Test in Europe Conference and Exhibition, California Univ., Berkeley ,CA ,USA. pp: 256-261.
- JianhuaHuang (2003) Network processor design, Proc. 5th Int. Conf. on ASIC2003, pp:26-33.
- Jing Fu Hagsand (2005) Designing and evaluating network processor applications. Workshop on high performance switching and routing. Institute of Technol. Kista, Sweden. pp:142-146.
- Lekkas P (2004) Network processor architectures, Protocol,platforms. McGraw-Hill.
- Niemann JG, Porrmam M and Ruckert U (2005) A scalable parallel SoC architecture for network processor. IEEE Computer society annual symposium on VLSI, Heinz Nixdorf Inst. Paderborn Univ., Germany, pp: 311-313.
- Noonan L (2004) Modeling a network processor using object oriented techniques. Euromicro Symposium on Digital System Design. Dept. of Electron. Eng. Limerrick Univ., Ireland. pp: 484-490.
- Spalink T, Karlin S, Peterson L and Gottlieb Y (2001) Building a robust software-based router using network processors. Proc. of the 18th ACM Symposium on Operating Systems Principles (SOSP01), Chateau Lake Louise, Banff, Alberta,Canada. October. pp:216-229,
- Wolf Tilman, Franklin mark (2006) Performance models for network processor design. IEEE Transact. on parallel and distributed systems.pp:548- 561.
- Wolf Tilman, Franklinmark E. Ayguade, Valero M and Navaux P (2006) A simulator for SMT architectures: Evaluating instruction cache topologies. 12th Symposium on Computer Architecture and High Performance Computing. pp: 279- 286.